周国清, 黄景金, 舒磊. 基于FPGA的P-H法星上解算卫星相对姿态[J]. 武汉大学学报 ( 信息科学版), 2018, 43(12): 1838-1846. DOI: 10.13203/j.whugis20180248
引用本文: 周国清, 黄景金, 舒磊. 基于FPGA的P-H法星上解算卫星相对姿态[J]. 武汉大学学报 ( 信息科学版), 2018, 43(12): 1838-1846. DOI: 10.13203/j.whugis20180248
ZHOU Guoqing, HUANG Jingjin, SHU Lei. An FPGA-Based P-H Method On-Board Solution for Satellite Relative Attitude[J]. Geomatics and Information Science of Wuhan University, 2018, 43(12): 1838-1846. DOI: 10.13203/j.whugis20180248
Citation: ZHOU Guoqing, HUANG Jingjin, SHU Lei. An FPGA-Based P-H Method On-Board Solution for Satellite Relative Attitude[J]. Geomatics and Information Science of Wuhan University, 2018, 43(12): 1838-1846. DOI: 10.13203/j.whugis20180248

基于FPGA的P-H法星上解算卫星相对姿态

An FPGA-Based P-H Method On-Board Solution for Satellite Relative Attitude

  • 摘要: 针对目前星上遥感图像实时处理只能实现低级别算法的情况,提出了基于现场可编程门阵列(field-programmable gate array,FPGA)的P-H法星上相对姿态实时解算模型。该模型不仅避免了传统基于欧拉角的复杂三角函数计算与初值估算,还降低了迭代次数。试验选用FPGA(V7 xc7vx1140t)作为实时解算的硬件平台。在FPGA实现中,采用64位的浮点数据结构和串行/并行相结合策略;并采用LU(Lower-Upper)分解-分块算法实现矩阵求逆。试验结果表明,该模型的迭代次数比基于欧拉角的少了13次。该模型在FPGA和计算机的实现结果相差仅为5.0×10-14,加速度比为10。另外,该模型可广泛适用于实时性要求高的图像处理领域。

     

    Abstract: Aimed at the situation that the low-level algorithms were implemented in satellite real time processing system for remote sensing image, this paper proposes an FPGA (field programmable gate array) -based P-H method for satellite relative attitude on-board solution. The proposed algorithm not only avoids computations of trigonometric function and estimation of initial value, but also reduces the number of iterations when comparing with the Eulerian angle-based algorithm. The Xilinx FPGA (V7 xc7vx1140tflg1930-1) is selected as the hardware platform for the real-time processing. In FPGA implementation:①We adopt a 64-bit floating point data structure and a strategy of combination of serial and parallel processing; ②a lower-upper (LU) decomposition-block algorithm is adopted for matrix inversion. The experimental results indicate that the number of iterations of the proposed algorithm is 13 less than the Eulerian angle-based algorithm. The difference of FPGA and PC implementation is about 5.0×10-14 and the speedup is about 10, which meets the requirements of precision and speed for on-board image real time processing. The proposed algorithm can be suitable for high real-time image processing field.

     

/

返回文章
返回